RISC CPU model

The provided example demonstrates a simple RISC CPU design.

The CPU is modeled in SystemC. The CPU reads in an assembly program and executes it. It then writes the result back to the registers. The instruction set is based on a commercial RISC processor together with MMX-like instruction for DSP programs. It consists of more than 39 instructions, including: arithmetic, logic, branch, floating point, and SIMD.

Algorithms are executed in the CPU and cycles can be measured. The behavior of the CPU and aspects of the memory can be modified by the user.

The memory data is initialized through these files:
abc.asm - sample program
bios - system bios data
dcache - initial data cache
icache - initial instruction cache
register - initial register values

SystemC files:
bios.cpp - system bios unit
dcache.cpp - data cache unit
decode.cpp - instruction decode unit, contains opcodes
exec.cpp - case switch on opcode_tmp's
fetch.cpp - instruction fetch unit
floating.cpp - floating point execution unit
icache.cpp - instruction cache unit
main.cpp - top level
mmxu.cpp - MMX-like execution unit
paging.cpp - instruction paging unit
pic.cpp - programmable interrupt unit