Transaction Level Model diagram
Michigan State University - Summer Research
Research of: Adaptive System-on-Chip (SoC) architectures, SystemC, reconfigurable hardware, adaptive wireless sensor networks, Xilinx Tools, MicroBLAZE, Cadence IC Design, VLSI, FPGAs, and ASICs.
1 Comments:
Hii joe,
I also work on the Transaction level modelling using SystemC at ST microelctronics. I would like to know more about your project and would like to be in touch.
Regards
Mohit
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