System Level Design

Processor + VHDL/Verilog blocks (peripherals)
Full level functionality at high-level -> SystemC
ISS: Instruction set simulator

Model:

FETCH - get instructions
MEMORY- data & code (not necessarily separated)
DECODE & EXEC- all in one
INTERRUPTS- non-preemptive
GPIO - integrated into memory manager
GPR - function-wise store data, access data

process {
fetch()
decode() // including exec & addl fetch
wait()
update() // reg & memory
}