SystemC Model Expansion

It was suggested that in order to create a good model that could be used in discussion in a possible paper, an analog sensor module could be added to the existing model. The module would include an analog source, an A/D interface, and a register map that connected to the existing bus. The MSP430 core could then verify the data received and convert the digital value into a more meaningful representation of the analog input (such as 2.5 V).

As an aside, research of the ARM AMBA (Advanced Microcontroller Bus Architecture), an open standard, on-chip bus specification. It is used in the development of multi-processor and multi-peripheral embedded processors ("a common backbone for SoC modules").

Also, research of materials for multi-processor designs can be found at OCPIP.org . OCP-IP (Open Core Protocol International Partnership) is "dedicated to making a common standard for intellectual property (IP) core interfaces, or sockets, that facilitate 'plug and play' System-on-Chip (SoC) design."

MSP430 SystemC Model

Still To Do (near future):

• byte mode (word mode implemented)
• DADD - a binary coded decimal (BCD) addition operation
• Testing to ensure correct output and status flags
• Use of gcc code flow to create machine code from C code
• Transaction level modeling of bus

MSP430 SystemC Model

The model now contains a memory module that serves as the 64K memory that the MSP430 uses. The addressing modes of the MSP430 are confusing - depending on which registers are used, the addressing mode bits mean different things. This allows the microcontroller to have 7 addressing modes available, while only being able to select out of a maximum of 4 at a time (depending on the operation type).

The initial thought that the MSP430 was RISC-like is becoming more and more dissolved as I continue. The addressing modes are an example of this. It may have only 27 instructions, but the addressing modes and other characteristics complicate this notion.

Most of the instructions are now working for the direct addressing mode. Work is continuing to make the other addressing modes perform correctly.

Xilinx Virtex-II PRO

I began working with the new Xilinx board that came in recently. The Virtex-II PRO (XC2P30) has two PowerPC Processors and is more powerful than the boards we normally use. The use of expansion boards such as DDR SDRAM will allow the board to grow with our applications. The board will primarily be used as a host for embedded processor cores and complex digital systems.

Virtex-II PRO FPGA

I installed the software that came with FPGA board. The EDK (Embedded Development Kit) is a set of tools for designing embedded processor systems using programmable logic, and supports the IBM PowerPC processors and the Xilinx MicroBlaze soft processor core. The main tool is the "Platform Studio". It integrates all of the steps from design entry to debugging and verification.

I began reading the "Platform Studio User Guide", provided by Xilinx, to learn how to create a basic embedded hardware system using one of the PowerPC cores.

The steps taken in creating a hardware system for EDK using the Xilinx Platform Studio (XPS) are:

1. Create a New XPS Project
2. Select a Target Board
3. Select the Processor to be Used
4. Configure the Processor
5. Configure IO Interfaces
6. Specify Internal Peripheral Settings
7. Specify Software Configuration
8. View System Summary and Generate
9. View Peripherals and Bus Settings
10. Generate Bitstream
11. Download Bitstream and Execute

System Level Design

Processor + VHDL/Verilog blocks (peripherals)
Full level functionality at high-level -> SystemC
ISS: Instruction set simulator

Model:

FETCH - get instructions
MEMORY- data & code (not necessarily separated)
DECODE & EXEC- all in one
INTERRUPTS- non-preemptive
GPIO - integrated into memory manager
GPR - function-wise store data, access data

process {
fetch()
decode() // including exec & addl fetch
wait()
update() // reg & memory
}