MSP430 Model

Work has continued in systemC to develop a model for the MSP430. I was told during a recent meeting that my previous work on the model was at the gate-level and needed to be at the system-level. However, the attempt has helped me become more familiar with systemC.

Planning was needed to layout the model. The instructions had to be decoded into the necessary parts such as the opcode, addressing mode, source, and destination. The status register was developed to be set by the appropriate executions.

RISC CPU model

The provided example demonstrates a simple RISC CPU design.

The CPU is modeled in SystemC. The CPU reads in an assembly program and executes it. It then writes the result back to the registers. The instruction set is based on a commercial RISC processor together with MMX-like instruction for DSP programs. It consists of more than 39 instructions, including: arithmetic, logic, branch, floating point, and SIMD.

Algorithms are executed in the CPU and cycles can be measured. The behavior of the CPU and aspects of the memory can be modified by the user.

The memory data is initialized through these files:
abc.asm - sample program
bios - system bios data
dcache - initial data cache
icache - initial instruction cache
register - initial register values

SystemC files:
bios.cpp - system bios unit
dcache.cpp - data cache unit
decode.cpp - instruction decode unit, contains opcodes
exec.cpp - case switch on opcode_tmp's
fetch.cpp - instruction fetch unit
floating.cpp - floating point execution unit
icache.cpp - instruction cache unit
main.cpp - top level
mmxu.cpp - MMX-like execution unit
paging.cpp - instruction paging unit
pic.cpp - programmable interrupt unit

MSP430 SystemC Model

I worked on creating the functions of the MSP430 in SystemC. After some experimentation, I arrived at a simplistic model for a function template that can be used for most of the functions. The MSP430 has 27 instructions ranging from logic functions to arithmetic functions to branch and jump instructions (among others). These simple instructions are the basic of the RISC model for the MSP430, and many more functions can be created from these instructions.

The list of instructions:

0100 MOV
0101 ADD
0110 ADDC
0111 SUBC
1001 SUB
1001 CMP
1010 DADD
1011 BIT
1100 BIC
1101 BIS
1110 XOR
1111 AND

000 JNE/JNZ
001 JEQ/Z
010 JNC/JLO
011 JC/JHS
100 JN
101 JGE
110 JL
111 JMP

000 RRC
001 SWPB
010 RRA
011 SXT
100 PUSH
101 CALL
110 RETI

Adaptive SoC Modeling and Design Objectives

1. Become familiar with SystemC and VHDL.
2. Write a SystemC model for MSP430 core (can simplify functions if difficulty exists).
3. Write the bus transaction level model (TLM) connecting 430 core.
4. Test multi-core processing and communication.
5. Model DVS (Dynamic Voltage Scaling) for different cores.
6. Create adaptive processing array model for streaming data (data flow modeling).

SystemC

I began working on a training course for SystemC called "Introduction to SystemC" by Forte Design Systems. It is a large tutorial designed to give a broad view of SystemC and its syntax. Example code is given; following each section is a short quiz.

The chapters include: Introduction to System C, Channels and Modules, Events and Processes, Structure, Modeling, and Functional Verification.

Chap1:
- Understand why C++ is inadequate and in general how SystemC addresses these inadequacies.
- Understand modeling terms and model types used in SystemC.
- Understand at a high level how SystemC systems and modules are put together.
- Understand at a high level the SystemC module communication paradigm.

Chap2:
- Learn SystemC provided data types and their usage.
- Understand SystemC communication behavior using interfaces, channels and ports.
- Learn the SystemC provided channels.
- Learn how to declare the structure of a module.

Chap3:
- Learn about Events, the basic SystemC synchronization object.
- Learn about SystemC Processes: Thread and Method.

First Day of Research at MSU

I arrived at MSU this morning and continued to work on tutorials and examples in SystemC and VHDL. Professor Zhong scheduled a meeting at 2:00 PM.

Research articles can be found at IEEE Xplore and ACM.org Portal. These two sites will provide additional information that is needed to research System-on-Chip designs and methods.

Professor Zhong suggested that I start with designing simple machines such as an array of ALUs. The two approaches are:

1. Model approach - SystemC, VHDL, Verilog (see Jimmy)
2. Prototype approach - FPGA, microBLAZE (embedded processor), MSP430

Modeling is better to start with first because the prototype/hardware approach would require too much reading of reference material before interesting results could be evaluated.

The overall goal is to study the Adaptive SoC design. It would use an embedded processor for most of computations, but hardware would be designed to handle processes that would benefit from parallelism. One example would be an MPEG decoder in hardware, which is more desirable than in software because of the continuous computation required.

Two questions were posed:

1. How to model concurrent processing?
2. How to model communication (channels, ports, etc...)?

I was encouraged to invent a process that uses several computers. The process would be light-weight and could be as basic as a few multipliers.

Professor Zhong also spoke about future topics that I would be able to pursue. One such topic was applications in signal analysis. It would look at a wireless sensor network. An example of research in this area would be to answer: "How to process data that requires significant computation time?". Aspects of fine-grain parallelism would play a role in this research. Also energy modeling would be of interest. Another topic suggested was Nanoscale devices and fabrication techniques.

Assigned Readings

4 technical papers were read. The titles are:

• "Five Ways to Design Future SoC"
• "MOGAC: A Multiobjective Genetic Algorithm for the Co-Synthesis of Hardware-Software Embedded Systems"
• "High-Level Power Analysis for On-Chip Networks"
• "Route Packets, Not Wires: On-Chip Interconnection Networks"

Start of a Summer Research Blog

The purpose of this blog is to record aspects of the research I complete during the summer of 2005.

The research will occur at Michigan State University in the Electrical and Computer Engineering Department. The faculty advisor will be Professor Zhong. Topics range from System-on-Chip (SoC) architectures, SystemC, Xilinx Tools, MicroBLAZE, Cadence IC Design, VLSI, FPGAs, and ASICs.